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FAST CMOS 18-BIT REGISTERED TRANSCEIVER Integrated Device Technology, Inc. IDT54/74FCT16500AT/CT/ET IDT54/74FCT162500AT/CT/ET bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit reg* Common features: istered bus transceivers combine D-type latches and D-type - 0.5 MICRON CMOS Technology flip-flops to allow data flow in transparent, latched and clocked - High-speed, low-power CMOS replacement for modes. Data flow in each direction is controlled by outputABT functions enable (OEAB and OEBA), latch enable (LEAB and LEBA) - Typical tSK(o) (Output Skew) < 250ps and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, - Low input and output leakage 1A (max.) the device operates in transparent mode when LEAB is HIGH. - ESD > 2000V per MIL-STD-883, Method 3015; When LEAB is LOW, the A data is latched if CLKAB is held at > 200V using machine model (C = 200pF, R = 0) a HIGH or LOW logic level. If LEAB is LOW, the A bus data is - Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. OEAB performs the output enable function on the B - Extended commercial range of -40C to +85C port. Data flow from B port to A port is similar but uses OEBA, - VCC = 5V 10% LEBA and CLKBA. Flow-through organization of signal pins * Features for FCT16500AT/CT/ET: simplifies layout. All inputs are designed with hysteresis for - High drive outputs (-32mA IOH, 64mA IOL) improved noise margin. - Power off disable outputs permit "live insertion" The FCT16500AT/CT/ET are ideally suited for driving - Typical VOLP (Output Ground Bounce) < 1.0V at high-capacitance loads and low-impedance backplanes. The VCC = 5V, TA = 25C output buffers are designed with power off disable capability * Features for FCT162500AT/CT/ET: to allow "live insertion" of boards when used as backplane - Balanced Output Drivers: 24mA (commercial), drivers. 16mA (military) The FCT162500AT/CT/ET have balanced output drive - Reduced system switching noise with current limiting resistors. This offers low ground bounce, - Typical VOLP (Output Ground Bounce) < 0.6V at minimal undershoot, and controlled output fall times-reducing VCC = 5V,TA = 25C the need for external series terminating resistors. The FCT162500AT/CT/ET are plug-in replacements for the DESCRIPTION: FCT16500AT/CT/ET and ABT16500 for on-board bus interThe FCT16500AT/CT/ET and FCT162500AT/CT/ET 18- face applications. FEATURES: FUNCTIONAL BLOCK DIAGRAM OEAB CLKBA LEBA OEBA CLKAB LEAB C A1 D C B1 D C D C D The IDT logo is a registered trademark of Integrated Device Technology, Inc. TO 17 OTHER CHANNELS 2548 drw 01 MILITARY AND COMMERCIAL TEMPERATURE RANGES (c)1996 Integrated Device Technology, Inc. AUGUST 1996 DSC-2548/7 5.9 1 IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND 2548 drw 02 OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E56-1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 2548 drw 03 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND SSOP/ TSSOP/TVSOP TOP VIEW CERPACK TOP VIEW 5.9 2 IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Pin Names OEAB Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input (Active LOW) B-to-A Clock Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs 2548 tbl 01 FUNCTION TABLE(1,4) Inputs LEAB CLKAB X H H L L L L X X X H L Outputs Bx Z L H L H B(2) B(3) OEBA LEAB LEBA OEAB L H H H H H H Ax X L H L H X X CLKAB CLKBA Ax Bx NOTES: 2548 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance = HIGH-to-LOW Transition ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND -0.5 to VTERM(3) Terminal Voltage with Respect to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120 Unit V V CAPACITANCE (TA = +25C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF 2548 lnk 04 C mA NOTE: 1. This parameter is measured at characterization but not tested. 2548 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT. 5.9 3 IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10% Symbol VIH VIL II H II L IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input Input LOW Current (I/O (3-State Output pins) (5) VCC = Min., IIN = -18mA VCC = Max., VO = GND (3) -- Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = GND VCC = Max. VO = 2.7V VO = 0.5V Min. 2.0 -- -- -- -- -- -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 Max. -- Unit V V A 0.8 1 1 1 1 1 1 -1.2 -225 -- pins)(5) pins)(5) High Impedance Output Current Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current A V mA mV A 100 5 VCC = Max., VIN = GND or VCC 500 2548 lnk 05 OUTPUT DRIVE CHARACTERISTICS FOR FCT16500T Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage Test Conditions(1) VCC = Max., VO = 2.5V(3) VCC = Min. VIN = VIH or VIL IOH = -3mA IOH = -12mA MIL. IOH = -15mA COM'L. IOH = -24mA MIL. IOH = -32mA COM'L.(4) VCC = Min. IOL = 48mA MIL. VIN = VIH or VIL IOL = 64mA COM'L. VCC = 0V, VIN or VO 4.5V Min. -50 2.5 2.4 2.0 -- -- Typ.(2) -- Max. -180 Unit mA V V V V A 2548 lnk 06 3.5 3.5 3.0 0.2 -- -- -- -- 0.55 1 VOL IOFF Output LOW Voltage Input/Output Power Off Leakage(5) OUTPUT DRIVE CHARACTERISTICS FOR FCT162500T Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -16mA MIL. IOH = -24mA COM'L. IOL = 16mA MIL. IOL = 24mA COM'L. Min. 60 -60 2.4 -- Typ.(2) 115 -115 3.3 0.3 Max. 200 -200 -- 0.55 Unit mA mA V V 2548 lnk 07 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C. 5.9 4 IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max., Outputs Open VIN = VCC OEAB = OEBA = VCC or GND VIN = GND One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = OEBA = VCC LEAB = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = OEBA = VCC LEAB = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND Min. -- -- Typ.(2) 0.5 75 Max. 1.5 120 Unit mA A/ MHz IC Total Power Supply Current(6) -- 0.8 1.7 mA VIN = 3.4V VIN = GND -- 1.3 3.2 VIN = VCC VIN = GND -- 3.8 6.5(5) VIN = 3.4V VIN = GND -- 8.5 20.8(5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 2548 tbl 08 5.9 5 IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT16500AT/162500AT Com'l. Symbol Parameter Mil. FCT16500CT/162500CT Com'l. Mil. FCT16500ET/162500ET Com'l. Mil. Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU CLKAB or CLKBA frequency(4) CL = 50pF -- 1.5 1.5 1.5 1.5 1.5 3.0 0 3.0 1.5 1.5 3.0 3.0 -- 150 5.1 5.6 5.6 6.0 5.6 -- -- -- -- -- -- -- 0.5 -- 1.5 1.5 1.5 1.5 1.5 3.0 0 3.0 1.5 1.5 3.0 3.0 -- 150 5.6 6.0 6.0 6.4 6.0 -- -- -- -- -- -- -- 0.5 -- 1.5 1.5 1.5 1.5 1.5 3.0 0 3.0 1.5 1.5 3.0 3.0 -- 150 4.6 5.3 5.3 5.6 5.2 -- -- -- -- -- -- -- 0.5 -- 1.5 1.5 1.5 1.5 1.5 3.0 0 3.0 1.5 1.5 3.0 3.0 -- 150 4.6 5.6 5.4 6.0 5.6 -- -- -- -- -- -- -- 0.5 -- -- -- -- -- -- 2.4 0 2.0 1.5 0.5 3.0 3.0 -- 150 3.8 4.2 4.2 4.8 4.0 -- -- -- -- -- -- -- 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 2548 tbl 09 Propagation Delay RL = 500 Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA tH Hold Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA tSU Set-up Time Clock HIGH or LOW HIGH Ax to LEAB, Clock Bx to LEBA LOW tH Hold Time, HIGH or LOW Ax to LEAB, Bx to LEBA tW LEAB or LEBA Pulse Width HIGH(4) tW CLKAB or CLKBA Pulse Width HIGH or LOW(4) tSK(o) Output Skew (3) NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested. 5.9 6 IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 2548 drw 04 SWITCH POSITION Test 7.0V Switch Open Drain Disable Low Enable Low All Other Tests Closed VOUT Open 500 2548 lnk 10 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU tH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 2548 drw 05 LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE 1.5V tREM 1.5V 2548 drw 06 tSU tH PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 0V 2548 drw 08 SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V 2548 drw 07 1.5V tPLZ 3.5V 1.5V tPHZ 0.3V VOH 0V 3.5V 0.3V VOL NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns 5.9 7 IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT X FCT XXXX Device Temperature Type Range X Package X Process Blank B PV PA PF E Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) 16500AT Non-Inverting 18-Bit Registered Transceiver 16500CT 16500ET 162500AT 162500CT 162500ET 54 74 -55C to +125C -40C to +85C 2548 drw 09 5.9 8 |
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